Small, low-power integrated circuits (ICs), such as application-specific ICs (ASICs) and application-specific standard products (ASSPs), are finding ever-increasing application in a wide variety of battery-powered, mobile devices. This is likely to continue and accelerate. Not only have these ICs begun to employ embedded memories, those memories are occupying an ever-increasing percentage of the total area of the IC. Embedded memories, including static random access memories (SRAM), consume power even when they are inactive.
Modern memories are equipped with one or more memory power management modes (e.g., standby, retention and power down modes) to reduce the power they consume while they are inactive. Memories are placed in a low-power mode until needed again. While in a low-power mode, they consume considerably less power and can significantly increase the duration of a battery charge.
ICs should be tested following manufacture to ensure their proper operation. For this reason, ICs are typically provided with a test access port (TAP) that conforms to Institute of Electrical and Electronics Engineers, Inc., (IEEE) 1149.1, or Joint Test Access Group (JTAG), standard. JTAG specifies a “boundary scanning” technique in which a tester (also called automated test equipment, or ATE) connected to the TAP via a JTAG (serial) bus provides one or more patterns of zeroes and ones (a “test pattern”) to the IC and receives a resulting (“output”) pattern of responses by the IC to the test pattern. An output pattern that does not match expectations indicates a failed test. The output pattern may be analyzed to determine the nature of the IC failure and perhaps where in the IC the failure occurred.
Manufacturing testing should extend to the one or more low-power modes that IC memories may be able to attain. Unfortunately, testing memory power management modes involves strict timing, which JTAG's limited bandwidth may not be able to maintain as memory sizes expand and speeds increase. What is needed in the art is a better way of testing memory power management modes in an IC.